Non-volatile semiconductor memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, the memory cell is electrically programmable and erasable by transporting charges in and out of a floating gate that is electrically insulated from but capacitively coupled to the surrounding electrodes. The amounts of charges retained in the floating gate define the states of a memory cell. Typically, the states thus defined can be either two levels or more than two levels (for multi-level states storage). The memory cell of such floating gate memory cells have been of the split gate type, or stacked gate type, or a combination thereof.
In current state-of-the-art nonvolatile memories, high voltage (typically ranging from 9 to 20V) is largely seen in cell operations (e.g. erase and program) in order to achieve desired memory states. Infrastructure for on-chip high voltage generation is thus essential to support the memory cell operations and has become an essential block in nonvolatile memories and products. The infrastructure involves separate sets of transistors used for handling high voltages and typically required adding at least 5 extra masks to a conventional CMOS technology. Therefore, it complicates process technology for nonvolatile memories.
Another issue on the high voltage infrastructure is its scalability along new generation technology. The high voltage is found un-scalable or difficult to be scaled due to the physics employed in memory cell operation. In a clear contrast, the operating voltage for logic circuits has been continuously scaled down in the past decades along with the scaling on minimum geometry of CMOS technology. An increasingly larger gap between voltages operating the logic circuits and the memory cells is seen. The issue is more pronounced and aggravated as CMOS technology scaled beyond 0.25 um generation. As a result, a larger overhead, in terms of the area occupied by high voltage circuitry, is often seen in newer generation memory products (in both stand-alone and embedded nonvolatile memory products). The scaling limit on high voltage further imposes constraints on the scaling of the minimum feature size for high-voltage transistors. Often, same sets of design rule for high-voltage transistors are used from one generation products to the next. Furthermore the high voltage operation introduces more issues in product functionality and reliability area.
U.S. Pat. No. 5,780,341 seek to overcome the problems by introducing a step channel/drain architecture into split gate type or stacked gate type cells, where electron charges are transported into floating gate through channel hot electron (CHE) or through source-side injection (SSI) mechanisms. The charges are transported out of floating gate through Fowler-Nordheim tunneling mechanism. However, the mechanisms thus involved require high voltages to support the operation. It was shown the step channel/drain cell structure can help achieving higher efficiency for charge injection. Given the efforts thus devoted, nevertheless, it was shown the voltage as high as 10V still be essential for cell operations. It is believed that the high voltage demands stringent control on the quality of the insulator surrounding the floating gate. The structures thus are vulnerable to manufacturing and reliability issues.
U.S. Pat. No. 6,372,617 seeks to minimize the high voltage by forming floating gate in concave shape through forming polycrystalline silicon spacers atop of floating gate edges. The floating gate architecture thus formed can maximize the capacitive coupling between control gate and floating gate electrodes. Similar effort has also been devoted on the same subject by maximizing floating gate area through forming hemispherical grained polycrystalline silicon on floating gate of concave shape, where high voltage in cell operation is shown reducible to around 16V. Kitamura T. et al., “A Low Voltage Operating Flash Cell with High Coupling Ratio Using Horned Floating Gate with HSG”, Symposium on VSLI Technology Dig. Technical Papers, pp. 104-105 (1998). However, the polycrystalline silicon spacer formation for concave floating gate adds complexity to the process. In addition, the large topography of the concave floating gate adds difficulty on subsequent process steps (e.g. word-line formation). Both make manufacturing be difficult. Furthermore, the concave floating gate architecture introduces larger step height around floating gate edge, which increase floating gate-to-floating gate interference and is in general against cell-to-cell spacing scaling.
Cell requirement on high voltage further impose constraints on its size scaling. For example, the high voltage handling capability of memory cells requires gate-length of a memory cell be long enough to avoid drain-to-source punch-through. As a result, it imposes scaling barriers on new generation technology, in terms of the minimum feature size on transistor length of a memory cell. Similar to the issues encountered in high voltage transistors, the issue in cell scaling is more pronounced and aggravated as technology scaled beyond 0.25 um generation. In terms of the cell physical size, the issue imposes a scaling constraint on the overall cell height (i.e. cell dimension defined in the direction of bit-line).
Another main issue on the memories scaling is the minimum thickness of the oxide encapsulating the floating gate. A theoretical value of 5-6 nm has been reported as the limit for an intrinsic oxide layer, in order to avoid charge leakage due to the Fowler-Nordheim tunneling. K. Naruke et al, “Stress Induced Leakage Current Limiting to Scale Down EEPROM Tunnel Oxide Thickness”, IEDM Technical Digest, pp. 424-427, 1988. However, extra leakage current often is induced after oxide dielectrics undergo a high voltage stress. As a result of this, to maintain the same level of low leakage and hence to retain stored charges within the floating gate per typical product specifications, it has been consistently reported that a minimum thickness of about 8-9 nm be used in production over several technology generations. S. Lai, “Flash Memories: Where We Were and Where We Are Going”, IEDM Technical Digest, pp. 971-973, 1998. This requirement on minimum oxide thickness limits the scalability of the cell channel width, when a minimum read current need be supplied from cells with a limited minimum gate-length. In terms of the cell physical size, the issue imposes a scaling constraint on the overall cell width (i.e. cell dimension defined in the direction of word-line).
The issues outlined above on cell size scaling are commonly seen in nonvolatile memory cells employing stacked gate EEPROM architecture, such as U.S. Pat. No. 4,957,877. Several proposals have been disclosed to overcome the obstacles for achieving a more compact cell size. U.S. Pat. No. 5,146,426 disclosed floating-gate and control-gate of memory cell formed in a “contact hole”-like trench, whereas, U.S. Pat. Nos. 5,432,739 and 5,563,083 disclosed floating-gate and the control-gate of memory cell formed along sidewall of a pillar-like silicon region. These types of cells can achieve significantly smaller cell size than those in stacked gate EEPROM of an equivalent generation technology. D. Kuo et al., “TEFET—A High Density, Low Erase Voltage, Trench Flash EEPROM”, Symposium on VSLI Technology Dig. Technical Papers, pp. 51-52 (1994); H. Pein et al, “Performance of the 3-D Sidewall Flash EPROM Cell”, IEDM Technical Digest, pp. 11-14 (1993). These cells however, require voltage higher than 12V for cell erase operation, and there are draw back yet to be overcome. For example, U.S. Pat. No. 5,146,426 use cells with buried source biased at high voltage for erase operation. A thinning on gate dielectric around the trench corner is proposed to form a localized high field enhancing charge transport therein during an erase operation. Given the efforts, the operating voltage is still quite high and a stringent control on the oxide integrity is deemed essential. In addition, a graded source junction is essential for this type of cell in order to sustain the high voltage. The high voltage in together with its operation through a buried source substantially adds limitations on achievable minimum spacing between the buried source regions and, therefore, restraints its future scaling. The constraints further complicate the memory array segmentation and block integration, which adversely enlarge the overall area of memory array, and therefore counteract its advantage on a smaller cell size. Furthermore, in U.S. Pat. No. 5,146,426, the trench bottom of each of the cells must be formed in the buried source within a tightly controlled depth in order for all the cells successfully operated during an erase operation. This stringent requirement is believed introducing significant manufacturing difficulties. U.S. Pat. Nos. 5,432,739 and 5,563,083 use pillar-like cell for compact cell size. This type of cell relies on large topography for floating gate and control gate formation, where polycrystalline silicon spacers are largely employed. Other than the draw back on needs for high voltage, it is generally believed that large topography and stringent condition for forming polycrystalline silicon spacers add process complexity, and hence make manufacturing difficult.